In digital devices located in the presence of relatively slow and/or noisy voltage ramps of input signals, due for instance to the use of pull-up transistors or to synchronization errors, spurious switching of a digital signal may occur. These undue switchings cause spurious pulses, hereinafter called “glitches”, that may compromise the proper functioning of the device.
To address this problem, input buffers with hysteresis are used. In some cases, this is not sufficient because the hysteresis is limited by specifications on the minimum voltage VIL and maximum voltage VIH, and, therefore, an excessively strong noise that may corrupt an input ramp jeopardizes the effort.
Similarly, the use of an RC filter connected at the output of the input filter, ensures only the filtering of glitches of a duration shorter than the response time of the filter. Moreover, it acts on both (leading and trailing) edges, thus it delays the acknowledging of the logic level of the input signal.
Clocked circuits for filtering glitches are disclosed in the literature. An example of such a clocked glitch filter is described in U.S. Pat. No. 6,535,057 and depicted in FIG. 1. This approach is burdened in general by the drawback of requiring a high frequency clock signal for obtaining the desired response. Moreover, the glitch filter is unsuitable for asynchronous applications.
Circuit architectures functioning without a clock signal have also been proposed. FIG. 2 shows a glitch filter disclosed in U.S. Pat. No. 6,392,474. In this known circuit, the noise input to the delay line 11 is filtered on one of the two branches of an SR latch. The latch is realized in a manner that will make it reliable even under a “Single Event Upset”, that is, it will correctly retain the current state even in presence of external events (radiation, electrical interference) that could make the latch switch. In this case, an input pulse lasting slightly longer than the delay introduced by the delay line 11 could cause an output glitch.
The circuit for filtering glitches illustrated in FIG. 3 and described in U.S. Pat. No. 6,670,832 addresses this problem. The external POR command forces the output signal OUT in an initial pre-defined state whatever is the logic level of the input PWM signal. When the POR command is not asserted, the logic values of the PWM signal cause the generation or not of pulses from the blocks ONE SHOT, which are transmitted through the filtering circuit to the flip-flop FFDR, that samples the input PWM signal in correspondence with the output edges of the logic gate 139.
The drawback of this known filtering circuit is that the output may be incoherent with the input if the input signal switches while the pulse is generated. Moreover, the filtering circuit has a relatively complex architecture.